module fifo_syn_rdaddr_gen(clk,
                           rst,
                           empty,
                           rd_en,
                           rd_addr,
                           wr_addr,wr_addr_r);
  input clk,rst,empty,rd_en;
  input [5:0] wr_addr;
  output [5:0]rd_addr;
  output [5:0]wr_addr_r; 
  reg [5:0] wr_addr_r;
  reg [5:0]rd_addr;
  wire clk,rst,empty,rd_en;
  
 always@(posedge clk or rst or empty or rd_en)
   begin
     if(!rst)
       begin
         rd_addr=0;
       end
     else
       begin
         if(empty)
           begin
             rd_addr=0;
           end
          else
             begin
               if(rd_en)
                 begin
                   rd_addr=rd_addr;//+1;
                   wr_addr_r=wr_addr-1;
                 end
             end
      end        
   end
endmodule
  
